Establish one canonical subject and follow it through every observable surface.

Prism separates the model's logical execution requirements from the hardware that will satisfy them. The ECS-native compiler preserves workload semantics while selecting mixed-precision representations, memory tiers, execution lanes, KV-cache policy, transfers, and validation gates for a particular target.

Scale line

• CPU — portable fallback, reference + hardening
• GPU — Metal or MI300X, ROCm / HIP execution
• NPU — XDNA / XDNA2, spatial plan + legality
• Handoff — KV ownership, residency + evidence

The serving requirement can stay constant while the physical plan changes. Prefill may run on one provider, KV state may cross an explicit boundary, and decode or streaming may run on another provider. The planner chooses a legal composition from capability descriptions rather than baking one vendor into the workload.

Phases

• Workload — Serve frontier model (latency, memory, quality policy)
• Phase 01 — Prefill (provider capability + admission)
• Handoff — KV transfer (explicit memory boundary)
• Phase 02 — Decode + stream (provider capability + receipt)

Researcher detail

The heterogeneous-serving fixture expresses a fixed serving requirement and provider phase capabilities for prefill, KV handoff, decode, and token streaming. Replacing the capability descriptions changes the plan without changing the serving requirement or orchestration contract.

Prism does not assume that a "GPU backend" is one universal target. A target profile constrains memory, bandwidth, scratch, resident views, context, sharding, KV ownership, and preferred execution lanes.

• CPU — Portable reference. Correctness oracle, fallback execution, and Linux hardening.
• GPU — Apple + MI300X. Metal on Apple Silicon; ROCm/HIP and gfx942-oriented validation on MI300X.
• NPU — XDNA / XDNA2. Tile, FIFO, DMA, barrier, and resource legalization for spatial plans.
• Heterogeneous — Cross-device plan. Route phases, activations, and KV state with explicit handoffs and evidence.

Prism does not pretend to be the accelerator.

Prism owns

• semantic workload
• physical plan
• KV ownership
• admission policy
• execution receipts

Provider owns

• kernels
• queues
• memory handles
• fabric transport
• device topology

Design constraint

Backend handles may execute work. They cannot silently become the authority for placement, lifecycle, or accepted outcome.

A single model family can have multiple deployment identities: a mixed-precision or ternarized CImage, a Metal or MI300X GPU image, an XDNA/XDNA2 spatial plan, or a heterogeneous composition with explicit KV-cache ownership. The logical model remains comparable while the physical artifact reflects the machine.

• Representation — FP16/BF16, INT8/NF4, progressive ternarization
• GPU — Metal or ROCm/HIP, MI300X validation
• NPU — XDNA/XDNA2, spatial legality
• State — KV search/compression, ownership + receipts

What is implemented today?

Apple Silicon and MI300X validation paths are active. ECS-native compilation, mixed-precision and ternary search, CImage assembly, and heterogeneous capability modeling are implemented across the repository. XDNA/XDNA2 planning is compile-verified and resource/legalization tested; general Ryzen AI hardware execution remains dependent on access to a matching XDNA-capable system and runtime stack.